The present application claims priority to Japanese Application No. P2000-157542 filed May 29, 2000, which application is incorporated herein by reference to the extent permitted by law.
1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device. More particularly, the present invention relates to a method of manufacturing a semiconductor device by forming a multilayered wiring construction by way of burying wiring material in recessed portions formed on an insulating film by applying a plating process.
2. Description of the Related Art
As a conventional practice, aluminum alloy has widely been used for composing wiring material of large-scale integrated circuits (LSIs). On the other hand, relative to such a growing demand for realizing finer construction and faster operating performance of the LSIs, actually, it has become difficult to secure such performance characteristics quite enough to realize higher reliability and lower resistivity via utilization of such wiring material made of aluminum alloy. To solve this problem, because of higher resistance to electro-migration and lower resistivity than those of aluminum alloy, an art for utilizing copper wiring has drawn attention, and yet, copper wiring has already been introduced to some semiconductor devices.
Generally, copper wiring can not easily be formed via a dry-etching process, and thus an art of forming copper wiring via slits is highly promising. In the art of forming copper wiring via slits, initially, predetermined slits are formed through an insulating film disposed between layers composed of silicon dioxide for example, and then, copper wiring material is buried into slits, and then, excessive copper wiring material is removed by applying a chemical-mechanical polishing process (called CMP process) to complete formation of a copper wiring structure inside of the slits.
Actually, a wide variety of methods have been introduced for burying copper wiring material inside of slits, which, for example, include the following: an electrolytic-plating method, a chemical vapor deposition (CVD) method, a sputtering reflow method, a high pressure-applied reflow method, a non-electrolytic plating method, or the like. Of those methods for burying copper wiring material inside of a slit as viewed from film forming speed, film forming cost, purity and adhesive property of metallic material to be formed, the above cited electrolytic plating method has mainly been utilized for manufacturing semiconductor devices.
An example of such a process for burying copper wiring material inside of slits and holes connecting them by execution of the electrolytic plating method is described below. Initially, tantalum nitride (TaN) is formed into a thin film having 30 nm of thickness for example, via a sputtering process. The TaN film functions itself as a barrier layer for preventing copper elements from being diffused into an inter-layer insulating film composed of silicon dioxide. Next, copper elements are formed into a thin film with 150 nm of thickness via a sputtering process. The formed copper film functions itself as a seed layer when copper elements are deposited thereon via an electrolytic plating process. Next copper elements are buried into slits via deposition by applying an electrolytic plating process.
Next, in order to form a copper wiring structure, excessive copper elements deposited on the inter-layer insulating film are removed. Conventionally, excessive copper deposits are removed via a chemical-mechanical polishing process. In place of the chemical mechanical polishing process, such a method is proposed, which etches back the copper surface by applying an electrolytic polishing process after completing an electrolytic plating process. While executing the electrolytic polishing process, anode of metallic surface is dissolved in specific solution to result in the generation of smooth and lustrous surface. Normally, the electrolytic polishing method has been used for eliminating debris from a surface of aluminum components and stainless steel components as well as for polishing them. In addition, the electrolytic polishing method has also been utilized for pre-treating copper components and copper-alloy components before actually plating them.
Nevertheless, in the case of introducing the above electrolytic polishing method for the process required for manufacturing semiconductor devices, execution of this method relies on such patterns formed on the surface of a substrate whereby causing such a differential step to be generated on the plated film. For example, as shown in FIG. 5, a plated film 113 generates recessed portion corresponding to such a differential step S in broad-width portion above an insulating film 111. On the other hand, the plated film 113 projects itself right above a plurality of slits 112N individually having a narrow width, thus also generating a differential step thereon.
Further, as shown in FIG. 6, because of the above differential steps, there is such a technical problem in which even such a plated film 113 that should have been held as the wiring material inside of a broad-width slit 112W formed in an insulating film 111 has been polished excessively on the way of executing an electrolytic polishing process. Conversely, there is another technical problem in which the plated film 113 still remains on such an area incorporating plural slits 112N each having a narrow width. As mentioned above, once such differential steps have locally been generated on a substrate 111, it will cause focal precision to be degraded in an exposure process while executing a lithographic process, for example, and yet, it will also cause the superimposing precision to be degraded. In addition, due to presence of the remained plated film 113 available for wiring material, short-circuit will be generated between wiring members formed between the narrow-width slits 112N as another problem to be solved.
In order to fully solve the above mentioned technical problems, the present invention hereby provides a novel method for manufacturing a semiconductor device.
A method for manufacturing a semiconductor device according to a first preferred embodiment of the present invention includes serial steps of an initial step of forming a wiring-material film for burying recessed portions formed in an insulating film formed on a substrate by applying a plating method; a second step of reducing differential steps locally generated on the surface of the above-referred wiring material film by way of preserving such wiring-material film corresponding to slit-formed portions above the insulating film; and a final step of removing the wiring-material film from the surface of the insulating film by applying an electrolytic polishing process while still preserving the buried wiring-material film solely inside of the recessed portions corresponding to the slit-formed portions.
By execution of the first inventive method described above, such differential steps locally generated on the surface of the wiring-material film are canceled while still preserving the required wiring-material film on the insulating film, whereby the surface of the wiring-material film is processed into a substantially flat condition. Next, the wiring-material film on the insulating film is removed by applying an electrolytic polishing process while still preserving the buried wiring material film solely inside of the recessed portions, whereby enabling the recessed portions to be filled with the buried wiring-material film, This in turn makes it possible to solely remove such wiring-material film deposited on unnecessary portions while still preserving such wiring-material film deposited in essential portions, thus enabling to properly form a wiring-structure inside of slits. In addition, since the electrolytic polishing method dispenses with expensive slurry normally used for executing a chemical mechanical polishing process, it is possible to form such a metallic wiring structure at a low running cost. Further, there is also an advantage in that the electrolytic polishing method also avoids generation of erosion normally occurring in the chemical mechanical polishing process.
A second method for manufacturing a semiconductor device according to a second preferred embodiment of the present invention includes the steps of an initial step of forming a wiring-material film via a plating process in order to bury recessed portions formed in an insulating film on a substrate by way of bearing such a thickness more than double the depth of the recessed portions; and a final step of removing the wiring-material film from the surface of the insulating film while still preserving the wiring-material film solely buried inside of the recessed portions.
Since the second preferred embodiment of the present invention described above forms such wiring-material film in order to bury recessed portions formed in the insulating film on the substrate by way of providing such thickness more than double the depth of the recessed portions, thus the surface of the resultant wiring-material film turns into a substantially flat surface. Further, by way of removing the wiring-material film from the surface of the insulating film while still preserving the wiring-material film solely buried inside of the recessed portions, the recessed portions are filled with the buried wiring material film. Accordingly, it is possible to remove such wiring-material film deposited on unnecessary portions while still preserving the wiring-material film deposited on essential portions, thus enabling to properly form such a wiring structure inside of recessed portions.
Further, inasmuch as the electrolytic polishing method dispenses with expensive slurry normally used for executing a chemical mechanical polishing process, it is possible to form a metallic-wiring structure at a low running cost. Further, there is also an advantage in that the electrolytic polishing method does not cause erosion that normally occurs in a chemical-mechanical polishing process.
As described above, according to the method for manufacturing a semiconductor device of the first preferred embodiment of the present invention, while executing an electrolytic polishing process following an electrolytic plating process, it is possible to remove such wiring-material film deposited on unnecessary portions by way of preserving such wiring-material film deposed on required portions, thus making it possible to introduce such an electrolytic polishing process for composing the wiring-material-filled slit structure. Since the electrolytic polishing process dispenses use of an expensive slurry normally used for executing a chemical-mechanical polishing process, it is possible to form a metallic-wiring structure at a low running cost. Further, unlike the chemical-mechanical polishing process, no erosion occurs in the course of executing the electrolytic polishing process.
According to the method for manufacturing a semiconductor device according to the second preferred embodiment of the present invention, since the wring-material film for burying a recessed portion is formed with such a thickness more than double the depth of the recessed portions, it is possible to polish the surface of the wiring-material film into substantially flat condition. Next, the wiring-material film deposited on an insulating film is removed by way of still preserving such wiring-material film deposited solely inside of the recessed portions, thus making it possible to solely remove such wiring-material film deposited on an unnecessary portion while still preserving such wiring-material film deposited on required portions to consequently make it possible to introduce such an electrolytic polishing process for providing a wiring-material-filled slit structure. Further, inasmuch as the electrolytic polishing process dispenses the expensive slurry normally used for executing the chemical-mechanical polishing process, it is possible to form a metallic-wiring structure at a low running cost. Further, there is such an advantage in that, unlike the case of the chemical-mechanical polishing process, the electrolytic polishing process is totally free from generating erosion.